Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 49
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Pipeline Architecture
MicroBlaze instruction execution is pipelined. For most instructions, each stage takes one
clock cycle to complete. Consequently, the number of clock cycles necessary for a specific
instruction to complete is equal to the number of pipeline stages, and one instruction is
completed on every cycle in the absence of data, control or structural hazards.
A data hazard occurs when the result of an instruction is needed by a subsequent
instruction. This can result in stalling the pipeline, unless the result can be forwarded to the
subsequent instruction. The MicroBlaze GNU Compiler attempts to avoid data hazards by
reordering instructions during optimization.
A control hazard occurs when a branch is taken, and the next instruction is not immediately
available. This results in stalling the pipeline. MicroBlaze provides delay slot branches and
the optional branch target cache to reduce the number of stall cycles.
A structural hazard occurs for a few instructions that require multiple clock cycles in the
execute stage or a later stage to complete. This is achieved by stalling the pipeline.
Load and store instructions accessing slower memory might take multiple cycles. The
pipeline is stalled until the access completes. MicroBlaze provides the optional data cache
to improve the average latency of slower memory.
When executing from slower memory, instruction fetches might take multiple cycles. This
additional latency directly affects the efficiency of the pipeline. MicroBlaze implements an
instruction prefetch buffer that reduces the impact of such multi-cycle instruction memory
latency. While the pipeline is stalled for any other reason, the prefetch buffer continues to
load sequential instructions speculatively. When the pipeline resumes execution, the fetch
stage can load new instructions directly from the prefetch buffer instead of waiting for the
instruction memory access to complete.
If instructions are modified during execution (for example with self-modifying code), the
prefetch buffer should be emptied before executing the modified instructions, to ensure
that it does not contain the old unmodified instructions.
RECOMMENDED: The recommended way to do this is using an MBAR instruction, although it is also
possible to use a synchronizing branch instruction, for example BRI 4.
MicroBlaze also provides the optional instruction cache to improve the average instruction
fetch latency of slower memory.
All hazards are independent, and can potentially occur simultaneously. In such cases, the
number of cycles the pipeline is stalled is defined by the hazard with the longest stall
duration.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module