Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 50
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Three Stage Pipeline
With C_AREA_OPTIMIZED set to 1 (Area), the pipeline is divided into three stages to
minimize hardware cost: Fetch, Decode, and Execute.
The three stage pipeline does not have any data hazards. Pipeline stalls are caused by
control hazards, structural hazards due to multi-cycle instructions, memory accesses using
slower memory, instruction fetch from slower memory, or stream accesses.
The multi-cycle instruction categories are barrel shift, multiply, divide and floating-point
instructions.
Five Stage Pipeline
With C_AREA_OPTIMIZED set to 0 (Performance), the pipeline is divided into five stages to
maximize performance: Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and
Writeback (WB).
The five stage pipeline has two kinds of data hazard:
• An instruction in OF needs the result from an instruction in EX as a source operand. In
this case, the EX instruction categories are load, store, barrel shift, multiply, divide, and
floating-point instructions. This results in a 1-2 cycle stall.
• An instruction in OF uses the result from an instruction in MEM as a source operand. In
this case, the MEM instruction categories are load, multiply, and floating-point
instructions. This results in a 1 cycle stall.
Pipeline stalls are caused by data hazards, control hazards, structural hazards due to multi-
cycle instructions, memory accesses using slower memory, instruction fetch from slower
memory, or stream accesses.
The multi-cycle instruction categories are divide and floating-point instructions.
cycle1 cycle2 cycle3 cycle4 cycle5 cycle6 cycle7
instruction 1 Fetch Decode Execute
instruction 2 Fetch Decode Execute Execute Execute
instruction 3 Fetch Decode
Stall Stall Execute
cycle1 cycle2 cycle3 cycle4 cycle5 cycle6 cycle7 cycle8 cycle9
instruction 1 IF OF EX MEM WB
instruction 2 IF OF EX MEM MEM MEM WB
instruction 3 IF OF EX
Stall Stall MEM WB
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module