Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 48
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Table 2-35: Processor Version Register 11 (PVR11)
Bits Name Description Value
0:1 MMU Use MMU: C_USE_MMU
0 = None
1 = User Mode
2 = Protection
3 = Virtual
2:4 ITLB Instruction Shadow TLB size log2(C_MMU_ITLB_SIZE)
5:7 DTLB Data Shadow TLB size log2(C_MMU_DTLB_SIZE)
8:9 TLBACC TLB register access: C_MMU_TLB_ACCESS
0 = Minimal
1 = Read
2 = Write
3 = Full
10:14 ZONES Number of memory protection zones C_MMU_ZONES
15 PRIVINS Privileged instructions:
0 = Full protection
1 = Allow stream instructions
C_MMU_PRIVILEGED_INSTR
16:16 Reserved Reserved for future use 0
17:31 RSTMSR Reset value for MSR C_RESET_MSR_IE << 2 |
C_RESET_MSR_BIP << 4 |
C_RESET_MSR_ICE << 6 |
C_RESET_MSR_DCE << 8 |
C_RESET_MSR_EE << 9 |
C_RESET_MSR_EIP << 10
Table 2-36: Processor Version Register 12 (PVR12)
Bits Name Description Value
0:31 VECTORS Location of MicroBlaze vectors C_BASE_VECTORS
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module