Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 47
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Table 2-30: Processor Version Register 6 (PVR6)
Bits Name Description Value
0:C_ADDR_SIZE-1 ICBA Instruction Cache Base Address C_ICACHE_BASEADDR
Table 2-31: Processor Version Register 7 (PVR7)
Bits Name Description Value
0:C_ADDR_SIZE-1 ICHA Instruction Cache High Address C_ICACHE_HIGHADDR
Table 2-32: Processor Version Register 8 (PVR8)
Bits Name Description Value
0:C_ADDR_SIZE-1 DCBA Data Cache Base Address C_DCACHE_BASEADDR
Table 2-33: Processor Version Register 9 (PVR9)
Bits Name Description Value
0:C_ADDR_SIZE-1 DCHA Data Cache High Address C_DCACHE_HIGHADDR
Table 2-34: Processor Version Register 10 (PVR10)
Bits Name Description Value
0:7 ARCH Target architecture: Defined by parameter
C_FAMILY
0xF = Virtex®-7, Defense Grade Virtex-7 Q
0x10 = Kintex®-7, Defense Grade Kintex-7 Q
0x11 = Artix®-7, Automotive Artix-7,
Defense Grade Artix-7 Q
0x12 = Zynq®-7000, Automotive Zynq-7000,
Defense Grade Zynq-7000 Q
0x13 = UltraScale™ Virtex
0x14 = UltraScale Kintex
0x15 = UltraScale+™ Zynq, Automotive
UltraScale+ Zynq
0x16 = UltraScale+ Virtex
0x17 = UltraScale+ Kintex
0x18 = Spartan®-7, Automotive Spartan-7
8:13 ASIZE Number of extended address bits C_ADDR_SIZE - 32
14:31 Reserved 0
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module