Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 82
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
When selecting cache sizes below 2 kB, distributed RAM is used to implement the Tag RAM
and Instruction RAM. Distributed RAM is always used to implement the Tag RAM, when
setting the parameter
C_ICACHE_FORCE_TAG_LUTRAM to 1. This parameter is only available
with cache size 8 kB and less for 4 word cache-lines, with 16 kB and less for 8 word cache-
lines, and with 32 kB and less for 16 word cache-lines.
For example: in a MicroBlaze configured with C_ICACHE_BASEADDR= 0x00300000,
C_ICACHE_HIGHADDR=0x0030ffff, C_CACHE_BYTE_SIZE=4096, C_ICACHE_LINE_LEN=8,
and
C_ICACHE_FORCE_TAG_LUTRAM=0; the cacheable memory of 64 kB uses 16 bits of byte
address, and the 4 kB cache uses 12 bits of byte address, thus the required address tag
width is: 16-12=4 bits. The total number of block RAM primitives required in this
configuration is: 2 RAMB16 for storing the 1024 instruction words, and 1 RAMB16 for 128
cache line entries, each consisting of: 4 bits of tag, 8 word-valid bits, 1 line-valid bit. In total
3 RAMB16 primitives.
The following figure shows the organization of Instruction Cache.
Instruction Cache Operation
For every instruction fetched, the instruction cache detects if the instruction address
belongs to the cacheable segment. If the address is non-cacheable, the cache controller
ignores the instruction and lets the
M_AXI_IP or LMB complete the request. If the address
is cacheable, a lookup is performed on the tag memory to check if the requested address is
currently cached. The lookup is successful if: the word and line valid bits are set, and the tag
address matches the instruction address tag segment. On a cache miss, the cache controller
requests the new instruction over the instruction AXI4 interface (
M_AXI_IC), and waits for
the memory controller to return the associated cache line.
C_ICACHE_DATA_WIDTH determines the bus data width, either 32 bits, an entire cache line
(128, 256 or 512 bits), or 512 bits.
X-Ref Target - Figure 2-22
Figure 2-22: Instruction Cache Organization
Tag Address Cache Address
Instruction Address Bits
- -
=
Tag
RAM
Line Addr
Tag
Valid (word and line)
Cache_Hit
Instruction
RAM
Word Addr
Cache_instruction_data
30 31
0
X19759-091317
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module