Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 124
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Use Cases
Several common use cases are described here. These use cases are derived from the
LogiCore IP Processor LMB BRAM Interface Controller Product Guide (PG112)
[Ref 3].
Minimal
This system is obtained when enabling fault tolerance in MicroBlaze, without doing any
other configuration.
The system is suitable when area constraints are high, and there is no need for testing of the
ECC function, or analysis of error frequency and location. No ECC registers are
implemented. Single bit errors are corrected by the ECC logic before being passed to
MicroBlaze. Uncorrectable errors set an error signal, which generates an exception in
MicroBlaze.
Small
This system should be used when it is necessary to monitor error frequency, but there is no
need for testing of the ECC function. It is a minimal system with Correctable Error Counter
Register added to monitor single bit error rates. If the error rate is too high, the scrubbing
rate should be increased to minimize the risk of a single bit error becoming an
uncorrectable double bit error. Parameters set are
C_ECC = 1 and C_CE_COUNTER_WIDTH =
10.
Typical
This system represents a typical use case, where it is required to monitor error frequency, as
well as generating an interrupt to immediately correct a single bit error through software. It
does not provide support for testing of the ECC function.
It is a small system with Correctable Error First Failing registers and Status register added. A
single bit error will latch the address for the access into the Correctable Error First Failing
Address Register and set the
CE_STATUS bit in the ECC Status Register. An interrupt will be
generated triggering MicroBlaze to read the failing address and then perform a read
followed by a write on the failing address. This will remove the single bit error from the
BRAM, thus reducing the risk of the single bit error becoming a uncorrectable double bit
error. Parameters set are:
-
C_ECC = 1
-
C_CE_COUNTER_WIDTH = 10
-
C_ECC_STATUS_REGISTER = 1
-
C_CE_FAILING_REGISTERS = 1
Send Feedback

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module