Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 123
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
perform all possible tests of the ECC function. See the SDK help [Ref 9] for more
information.
The self-test example can be found in the standalone BSP BRAM driver source code,
typically in the subdirectory
microblaze_0/libsrc/bram_v3_03_a/src/xbram_selftest.c.
Scrubbing
Scrubbing Methods
Scrubbing is performed using specific methods for the different block RAMs:
• Instruction and data caches: All lines in the caches are cyclically invalidated using the
WIC and WDC instructions respectively. This forces the cache to reload the cache line
from external memory.
• Memory Management Unit UTLB: All entries in the UTLB are cyclically invalidated by
writing the TLBHI register with the valid bit cleared.
• Branch Target Cache: The entire BTC is invalided by doing a synchronizing branch, BRI 4.
• LMB block RAM: All addresses in the memory are cyclically read and written, thus
correcting any single bit errors on each address.
It is also possible to add interrupts for correctable errors from the LMB BRAM Interface
Controllers, and immediately scrub this address in the interrupt handler, although in most
cases it only improves reliability slightly.
The failing address can be determined by reading the Correctable Error First Failing Address
Register in each of the LMB BRAM Interface Controllers.
To be able to generate an interrupt C_ECC_STATUS_REGISTERS must be set to 1 in the
connected LMB BRAM Interface Controllers, and to read the failing address
C_CE_FAILING_REGISTERS must be set to 1.
Calculating Scrubbing Rate
The scrubbing rate depends on failure intensity and desired reliability.
The approximate equation to determine the LMB memory scrubbing rate is in our case
given by
where P
W
is the probability of an uncorrectable error in a memory word, BER is the soft error
rate for a single memory bit, and SR is the Scrubbing Rate.
The soft error rates affecting block RAM for each product family can be found in the Device
Reliability Report User Guide (UG116)
[Ref 5].
P
W
760
2
BER
SR
2
------------



≈
Send Feedback

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module