Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 122
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
/*
* Start the interrupt controller such that interrupts are enabled for
* all devices that cause interrupts, specifying real mode so that the
* timer counter can cause interrupts thru the interrupt controller.
*/
Status = XIntc_Start(&InterruptController, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Setup the handler for the timer counter that will be called from the
* interrupt context when the timer expires, specify a pointer to the
* timer counter driver instance as the callback reference so the
* handler is able to access the instance data
*/
XTmrCtr_SetHandler(&TimerCounterInst, MicroBlazeScrubHandler,
&TimerCounterInst);
/*
* Enable the interrupt of the timer counter so interrupts will occur
* and use auto reload mode such that the timer counter will reload
* itself automatically and continue repeatedly, without this option
* it would expire once only
*/
XTmrCtr_SetOptions(&TimerCounterInst, TIMER_CNTR_0,
XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION);
/*
* Set a reset value for the timer counter such that it will expire
* earlier than letting it roll over from 0, the reset value is loaded
* into the timer counter when it is started
*/
XTmrCtr_SetResetValue(TmrCtrInstancePtr,TmrCtrNumber,SCRUB_PERIOD);
/*
* Start the timer counter such that it's incrementing by default,
* then wait for it to timeout a number of times
*/
XTmrCtr_Start(&TimerCounterInst, TIMER_CNTR_0);
...
}
See the section Scrubbing for further details on how scrubbing is implemented, including
how to calculate the scrubbing rate.
BRAM Driver
The standalone BSP BRAM driver is used to access the ECC registers in the LMB BRAM
Interface Controller, and also provides a comprehensive self test.
By implementing the SDK Xilinx C Project "Peripheral Tests", a self-test example including
the BRAM self test for each LMB BRAM Interface Controller in the system is generated.
Depending on the ECC features enabled in the LMB BRAM Interface Controller, this code will
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module