Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 312
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
Table A-12: Parameter Configurations
Parameter
Configuration Parameter Values
Microcontroller
Preset
Real-time
Preset
Application
Preset
Minimum
Area
Maximum
Performance
Maximum
Frequency
Linux
with MMU
Low-end Linux
with MMU
Typical
Frequency
Optimized
C_ALLOW_DCACHE_WR
1 1 1 1 1 1 1 1 1 1
C_ALLOW_ICACHE_WR
1 1 1 1 1 1 1 1 1 1
C_AREA_OPTIMIZED
1 0 0 1 0 0 0 0 0 2
C_CACHE_BYTE_SIZE
4096 8192 32768 4096 32768 4096 16384 8192 8192 16384
C_DCACHE_BYTE_SIZE
4096 8192 32768 4096 32768 4096 16384 8192 8192 16384
C_DCACHE_LINE_LEN
4 4 4 4 8 4 4 4 4 4
C_DCACHE_USE_WRITEBACK
0 1 1 0 1 0 0 0 0 1
C_DEBUG_ENABLED
1 1 1 0 1 0 1 1 1 1
C_DIV_ZERO_EXCEPTION
0 1 1 0 0 0 1 0 0 1
C_M_AXI_D_BUS_EXCEPTION
0 1 1 0 0 0 1 1 1 1
C_FPU_EXCEPTION
0 0 1 0 0 0 0 0 0 1
C_FSL_EXCEPTION
0 0 0 0 0 0 0 0 0 0
C_FSL_LINKS
0 0 0 0 0 1 0 0 0 0
C_ICACHE_LINE_LEN
4 4 8 4 8 4 8 4 8 8
C_ILL_OPCODE_EXCEPTION
0 1 1 0 0 0 1 1 0 1
C_M_AXI_I_BUS_EXCEPTION
0 1 1 0 0 0 1 1 0 1
C_MMU_DTLB_SIZE
2 2 4 2 4 2 4 4 4 4
C_MMU_ITLB_SIZE
1 1 2 1 2 1 2 2 2 2
C_MMU_TLB_ACCESS
3 3 3 3 3 3 3 3 3 3
C_MMU_ZONES
2 2 2 2 2 2 2 2 2 2
C_NUMBER_OF_PC_BRK
1 2 2 0 1 1 1 1 2 1
C_NUMBER_OF_RD_ADDR_BRK
0 0 1 0 0 0 0 0 0 0
C_NUMBER_OF_WR_ADDR_BRK
0 0 1 0 0 0 0 0 0 0
C_OPCODE_0x0_ILLEGAL
0 1 1 0 0 0 1 1 0 1
C_PVR
0 0 2 0 0 0 2 0 0 2
C_UNALIGNED_EXCEPTIONS
0 1 1 0 0 0 1 1 0 1
C_USE_BARREL
1 1 1 0 1 0 1 1 1 1
C_USE_DCACHE
0 1 1 0 1 0 1 1 1 1
C_USE_DIV
0 1 1 0 1 0 1 0 0 1
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module