Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 311
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
Table A-11: Device Utilization - Zynq UltraScale+ FPGAs (XCZU9EG ffvb1156-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1119 829 556
Real-time Preset 2479 2113 417
Application Preset 4417 3743 364
Minimum Area 563 225 669
Maximum Performance 4198 3195 370
Maximum Frequency 1100 553 669
Linux with MMU 3562 3124 366
Low-end Linux with MMU 3071 2493 394
Typical 2066 1673 453
Frequency Optimized 5965 5766 420
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module