Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 310
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
Table A-9: Device Utilization - Virtex UltraScale+ FPGAs (XCVU3P ffvc1517-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1107 825 553
Real-time Preset 2464 2121 417
Application Preset 4422 3745 348
Minimum Area 558 225 714
Maximum Performance 4188 3195 348
Maximum Frequency 1100 553 714
Linux with MMU 3546 3115 375
Low-end Linux with MMU 3067 2503 388
Typical 2058 1672 399
Frequency Optimized 5964 5748 416
Table A-10: Device Utilization - Kintex UltraScale+ FPGAs (XCKU15P ffva1156-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1107 813 590
Real-time Preset 2475 2113 411
Application Preset 4419 3741 354
Minimum Area 561 225 641
Maximum Performance 4182 3195 374
Maximum Frequency 1117 557 641
Linux with MMU 3544 3119 359
Low-end Linux with MMU 3071 2493 374
Typical 2068 1672 453
Frequency Optimized 5947 5748 424
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module