Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 309
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
Table A-7: Device Utilization - Virtex UltraScale FPGAs (XCVU095 ffvd1924-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1109 813 385
Real-time Preset 2446 2114 293
Application Preset 4394 3728 250
Minimum Area 578 231 476
Maximum Performance 4126 3206 274
Maximum Frequency 1103 558 476
Linux with MMU 3484 3113 262
Low-end Linux with MMU 3053 2500 266
Typical 2042 1672 317
Frequency Optimized 5938 5773 293
Table A-8: Device Utilization - Kintex UltraScale FPGAs (XCKU040 ffva1156-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1105 813 397
Real-time Preset 2444 2120 306
Application Preset 4394 3741 252
Minimum Area 578 242 461
Maximum Performance 4139 3196 280
Maximum Frequency 1099 558 461
Linux with MMU 3474 3131 248
Low-end Linux with MMU 3046 2497 262
Typical 2054 1676 315
Frequency Optimized 5947 5795 288
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module