Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 173
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
Table 3-17: Mapping of Trace MSR
Trace_MSR_Reg Machine Status Register
Bit Bit Name Description
0 17 VMS
Virtual Protected Mode Save
1 18 VM
Virtual Protected Mode
2 19 UMS
User Mode Save
3 20 UM
User Mode
4 21 PVR
Processor Version Register exists
5 22 EIP
Exception In Progress
6 23 EE
Exception Enable
7 24 DCE
Data Cache Enable
8 25 DZO
Division by Zero or Division Overflow
9 26 ICE
Instruction Cache Enable
10 27 FSL
AXI4-Stream Error
11 28 BIP
Break in Progress
12 29 C
Arithmetic Carry
13 30 IE
Interrupt Enable
14 31 Reserved
Reserved
Table 3-18: Type of Trace Exception
Trace_Exception_Kind [0:4] Description
00000
Stream exception
00001
Unaligned exception
00010
Illegal Opcode exception
00011
Instruction Bus exception
00100
Data Bus exception
00101
Divide exception
00110
FPU exception
00111
Privileged instruction exception
01010
Interrupt
01011
External non maskable break
01100
External maskable break
10000
Data storage exception
10001
Instruction storage exception
10010
Data TLB miss exception
10011
Instruction TLB miss exception
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module