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General| Architecture | 32-bit RISC |
|---|---|
| Cache | Configurable Instruction and Data Cache |
| Category | Soft Processor Core |
| Data Width | 32-bit |
| Memory Management Unit (MMU) | Optional |
| Floating Point Unit (FPU) | Optional |
| Interrupt Controller | Configurable |
| Memory Management | Optional MMU |
| Configurability | Highly Configurable |
| Pipeline Stages | 3-stage |
| FPGA Integration | Xilinx FPGAs |
| Bus Interface | PLB |
| Debug Interface | JTAG |
| Typical Clock Speed | Varies depending on FPGA and configuration (e.g., 100-400+ MHz) |
| Implementation | Soft core (synthesized logic) |
| Maximum Performance | Varies with FPGA and configuration |
| Debug Support | Integrated Debug Module |
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