Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 303
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
xori
Logical Exclusive OR with Immediate
xori
rD, rA, IMM
1 0 1 0 1 0 rD rA IMM
0 6 11 16
31
Description
The IMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register
rA are XOR’ed with the extended IMM field; the result is placed into register rD.
Pseudocode
(rD) ← (rA) ⊕ sext(IMM)
Registers Altered
•rD
Latency
• 1 cycle
Notes
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use
as the immediate operand. This behavior can be overridden by preceding the Type B instruction with
an imm instruction. See the instruction
“imm” for details on using 32-bit immediate values.
When this instruction is used with rD set to r0, a program trace event is emitted with the 14 least
significant bits of the result. Typically this is used to trace operating system events like context
switches and system calls, but it can be used by any program to trace significant events. The
functionality is enabled by setting C_DEBUG_ENABLED = 2 (Extended) and C_DEBUG_TRACE_SIZE > 0.
See
“Program and Event Trace” in Chapter 2 for further details.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module