Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 241
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
imm
Immediate
imm
IMM
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 IMM
0 6 11 16
31
Description
The instruction imm loads the IMM value into a temporary register. It also locks this value so it can be
used by the following instruction and form a 32-bit immediate value.
The instruction imm is used in conjunction with Type B instructions. Since Type B instructions have
only a 16-bit immediate value field, a 32-bit immediate value cannot be used directly. However, 32-bit
immediate values can be used in MicroBlaze. By default, Type B Instructions will take the 16-bit IMM
field value and sign extend it to 32 bits to use as the immediate operand. This behavior can be
overridden by preceding the Type B instruction with an imm instruction. The imm instruction locks the
16-bit IMM value temporarily for the next instruction. A Type B instruction that immediately follows
the imm instruction will then form a 32-bit immediate value from the 16-bit IMM value of the imm
instruction (upper 16 bits) and its own 16-bit immediate value field (lower 16 bits). If no Type B
instruction follows the imm instruction, the locked value gets unlocked and becomes useless.
Latency
• 1 cycle
Notes
The imm instruction and the Type B instruction following it are atomic; consequently, no interrupts are
allowed between them.
The assembler provided by Xilinx® automatically detects the need for imm instructions. When a 32-
bit IMM value is specified in a Type B instruction, the assembler converts the IMM value to a 16-bit
one to assemble the instruction and inserts an imm instruction before it in the executable file.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module