Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 242
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
lbu
Load Byte Unsigned
lbu
rD, rA, rB
lbur
rD, rA, rB
lbuea
rD, rA, rB
1 1 0 0 0 0 rD rA rB 0 R 0 EA 0 0 0 0 0 0 0
0 6 11 16 21
31
Description
Loads a byte (8 bits) from the memory location that results from adding the contents of registers rA
and rB. The data is placed in the least significant byte of register rD and the other three bytes in rD are
cleared.
If the R bit is set, a byte reversed memory location is used, loading data with the opposite endianness
of the endianness defined by the E bit (if virtual protected mode is enabled).
If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding
them.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This
only applies to accesses with user mode and virtual protected mode enabled.
A privileged instruction error occurs if the EA bit is set, Physical Address Extension (PAE) is enabled,
and the instruction is not explicitly allowed.
Pseudocode
if EA = 1 then
Addr
← (rA) & (rB)
else
Addr ← (rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]
← 10010;ESR[S]← 0
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
ESR[EC]
← 10000;ESR[S]← 0; ESR[DIZ] ← 1
MSR[UMS] ← MSR[UM]; MSR[VMS] ← MSR[VM]; MSR[UM] ← 0; MSR[VM] ← 0
else
(rD)[24:31]
← Mem(Addr)
(rD)[0:23] ← 0
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module