Xilinx MicroBlaze - Page 239

MicroBlaze Processor Reference Guide 240
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
idiv
Integer Divide
idiv
rD, rA, rB
divide rB by rA (signed)
idivu
rD, rA, rB
divide rB by rA (unsigned)
0 1 0 0 1 0 rD rA rB 0 0 0 0 0 0 0 0 0 U 0
0 6 11 16 21
31
Description
The contents of register rB is divided by the contents of register rA and the result is placed into
register rD.
If the U bit is set, rA and rB are considered unsigned values. If the U bit is clear, rA and rB are
considered signed values.
If the value of rA is 0 (divide by zero), the DZO bit in MSR will be set and the value in rD will be 0,
unless an exception is generated.
If the U bit is clear, the value of rA is -1, and the value of rB is -2147483648 (divide overflow), the DZO
bit in MSR will be set and the value in rD will be -2147483648, unless an exception is generated.
Pseudocode
if (rA) = 0 then
(rD) <- 0
MSR[DZO] <- 1
ESR[EC] <- 00101
ESR[DEC] <- 0
else if U = 0 and (rA) = -1 and (rB) = -2147483648 then
(rD) <- -2147483648
MSR[DZO] <- 1
ESR[EC] <- 00101
ESR[DEC] <- 1
else
(rD)
← (rB) / (rA)
Registers Altered
• rD, unless a divide exception is generated, in which case the register is unchanged
• MSR[DZO], if divide by zero or divide overflow occurs
• ESR[EC], if divide by zero or divide overflow occurs
Latency
• 1 cycle if (rA) = 0, otherwise 34 cycles with C_AREA_OPTIMIZED=0
• 1 cycle if (rA) = 0, otherwise 35 cycles with
C_AREA_OPTIMIZED=1
• 1 cycle if (rA) = 0, otherwise 30 cycles with
C_AREA_OPTIMIZED=2
Note
This instruction is only valid if MicroBlaze is configured to use a hardware divider (C_USE_DIV = 1).
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