Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 105
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Program and Event Trace
With extended debugging, MicroBlaze provides program and event trace, either storing
information in the Embedded Trace Buffer or transmitting it to the MDM, to enable program
execution tracing. The MDM is used when the parameter
C_DEBUG_EXTERNAL_TRACE is set,
allowing output of program trace from multiple processors using external interfaces.
The size of the Embedded Trace Buffer can be configured from 8KB to 128KB using the
parameter
C_DEBUG_TRACE_SIZE. The default buffer size with external trace is 8KB, but it
can also be configured from 32B to 256B to use distributed RAM. It is recommended to
always keep the default 8KB size, unless block RAM resources are very scarce. By setting
C_DEBUG_TRACE_SIZE to 0 (None), program trace is disabled.
Program trace uses compression to reduce the amount of trace data, while still allowing
reconstruction of the program execution flow or the entire processor software state. There
are three main compression levels:
• Complete trace: Stores complete trace information including cycle count for each
executed instruction using 144 bits, ranging from 512 to 8192 items depending on the
configured Embedded Trace Buffer size. Complete trace is not available when
C_DEBUG_EXTERNAL_TRACE is set.
• Program flow: Stores program flow changes, that is the sequence of branches taken or
not taken, and the new program counter for indirect branches, interrupts, exceptions
and hardware breaks.
The program counter can also optionally be stored for return instructions to simplify
program flow reconstruction, or for all taken branches to handle self-modifying code.
Data read from memory or fetched from AXI4-Stream interfaces might optionally be
stored to allow reconstructing the entire processor software state, enabling reverse
single step functionality. When the data access instruction is in a delay slot of a dynamic
branch or return, the data is stored first followed by the branch target program counter.
For data access instructions in delay slots of static branches, the program flow change is
first saved followed by the data.
Events representing all program exceptions, interrupts, and breaks, as well as all cross-
trigger events defined in Table 2-62 are also stored, to allow unambiguous decoding of
program flow changes. Each event is preceded by a stored program counter.
Software can inject an event by using an “xori r0, rN, IMM” instruction. Typically this is
used to trace operating system events like context switches and system calls, but it can
be used by any program to trace significant events.
• Program flow and cycle count: Stores the cycle count between instructions along with
the same information as program flow alone, to also allow reconstruction of the
program execution time.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module