Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 104
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Performance Counter Data Write Register
The Performance Counter Data Write Register (PCDWR) writes initial values to the counters.
To write all configured counters, the register should be written repeatedly. This register is a
write-only register. Issuing a read request has no effect, and undefined data is read.
Since a counter can have more than 32 bits, depending on the configuration, the register
might need to be written repeatedly to update all information for a particular counter, as
described in
Table 2-47.
X-Ref Target - Figure 2-30
Figure 2-30: Performance Counter Data Write Register
0
Item
31
X19766-082517
Table 2-48: Performance Counter Data Write Register (PCDWR)
Bits Name Description Reset Value
31:0 Item
Counter value item to write into a counter
0
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module