Xilinx MicroBlaze - Page 103

MicroBlaze Processor Reference Guide 103
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
C_DEBUG_COUNTER_WIDTH = 48
Event Counter
1
31:16
15:0
0x0000
The number of times the event occurred, 16 most significant bits
2
The number of times the event occurred, 32 least significant bits
Latency Counter
1
The number of times the event occurred
2
31:16
15:0
0x0000
The sum of each event latency, 16 most significant bits
3
The sum of each event latency, 32 least significant bits
4
31:16
15:0
0x0000
The sum of each event latency squared, 16 most significant bits
5
The sum of each event latency squared, 32 least significant bits
6
Minimum measured latency, 32 bits
7
Maximum measured latency, 32 bits
C_DEBUG_COUNTER_WIDTH = 64
Event Counter
1
The number of times the event occurred, 32 most significant bits
2
The number of times the event occurred, 32 least significant bits
Latency Counter
1
The number of times the event occurred, 32 bits
2
The sum of each event latency, 32 most significant bits
3
The sum of each event latency, 32 least significant bits
4
The sum of each event latency squared, 32 most significant bits
5
The sum of each event latency squared, 32 least significant bits
6
Minimum measured latency, 32 bits
7
Maximum measured latency, 32 bits
Table 2-47: Performance Counter Data Items (Cont’d)
Counter Type Item Description
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