Xilinx MicroBlaze - Page 102

MicroBlaze Processor Reference Guide 102
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Performance Counter Data Read Register
The Performance Counter Data Read Register (PCDRR) reads the sampled values of the
counters. To read the values of all configured counters, the register should be read
repeatedly. This register is a read-only register. Issuing a write request to the register does
nothing.
See the following figure and table.
Because a counter can have more than 32 bits, depending on the configuration, the register
might need to be read repeatedly to retrieve all information for a particular counter. This is
detailed in
Table 2-47.
Table 2-45: Performance Counter Status Register (PCSR)
Bits Name Description Reset Value
1Overflow
This bit is set when the counter has counted past its maximum value
0
0Full
This bit is set when a new latency counter event is started before the
previous event has finished. This indicates that the accuracy of the
measured values is reduced.
0
X-Ref Target - Figure 2-29
Figure 2-29: Performance Counter Data Read Register
0
Item
31
X19765-091117
Table 2-46: Performance Counter Data Read Register (PCDRR)
Bits Name Description Reset Value
31:0 Item
Sampled counter value item
0
Table 2-47: Performance Counter Data Items
Counter Type Item Description
C_DEBUG_COUNTER_WIDTH = 32
Event Counter
1
The number of times the event occurred
Latency Counter
1
The number of times the event occurred
2
The sum of each event latency
3
The sum of each event latency squared
4
31:16
15:0
Minimum measured latency, 16 bits
Maximum measured latency, 16 bits
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