Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 101
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Performance Counter Command Register
The Performance Counter Command Register (PCCMDR) is used to issue commands to
clear, start, stop, or sample all counters. This register is a write-only register. Issuing a read
request has no effect, and undefined data is read.
Performance Counter Status Register
The Performance Counter Status Register (PCSR) reads the sampled status of the counters.
To read the status for all configured counters, the register should be read repeatedly for
each of the counters. This register is a read-only register. Issuing a write request to the register
does nothing.
Every time the register is read, the selected counter is incremented. By using the
Performance Counter Command Register, the selected counter can be reset to the first
counter again. See
Figure 2-28 and Table 2-45.
X-Ref Target - Figure 2-27
Figure 2-27: Performance Counter Command Register
04
RES
Reserved
31
5
321
SAM
STOP
STACLR
X19763-091117
Table 2-44: Performance Counter Command Register (PCCMDR)
Bits Name Description Reset Value
4Clear
Clear all counters to zero
0
3Start
Start counting configured events for all counters simultaneously
0
2Stop
Stop counting all counters simultaneously
0
1Sample
Sample status and values in all counters simultaneously for reading
0
0 Reset
Reset accessed counter to the first event counter for access using the
Performance Counter Control, Status, Read Data and Write Data
0
X-Ref Target - Figure 2-28
Figure 2-28: Performance Counter Status Register
0
FULL
Reserved
31 21
OF
X19764-082517
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module