Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 131
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Both interfaces issue the following subset of the possible Distributed Virtual Memory
(DVM) transactions:
•DVM Operation
-
TLB Invalidate: Hypervisor TLB Invalidate by VA
-
Branch Predictor Invalidate: L Branch Predictor Invalidate all
-
Physical Instruction Cache Invalidate: Non-secure Physical Instruction Cache
Invalidate by PA without Virtual Index
-
Virtual Instruction Cache Invalidate: Hypervisor Invalidate by VA
•DVM Sync
-
Synchronization
•DVM Complete
-
In addition to the DVM transactions above, the interfaces only accept the
CleanInvalid and MakeInvalid transactions. These transactions have no effect in
the instruction cache, and invalidate the indicated data cache lines. If any other
transactions are received, the behavior is undefined.
-
Only a subset of AXI4 transactions are utilized by the interfaces, as described in
Cache Interfaces.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module