Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 130
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
After a MicroBlaze core has invalidated one or more entries, it must execute a memory
barrier instruction (MBAR), to ensure that all peer processors have completed their TLB
invalidation.
• Branch Target Cache invalidation: When a MicroBlaze core in the coherency domain
invalidates the Branch Target Cache, either with a memory barrier instruction or with a
synchronizing branch, hardware messages ensure that all other cores in the coherency
domain will do the same.
In particular, this means that self-modifying code can be used transparently within the
coherency domain in a multi-processor system, provided that the guidelines in
Self-
modifying Code are followed.
Protocol Compliance
The MicroBlaze instruction cache interface issues the following subset of the possible ACE
transactions:
• ReadClean: Issued when a cache line is allocated.
• ReadOnce: Issued when the cache is off, or if the MMU Inhibit Caching bit is set for the
cache line.
The MicroBlaze data cache interface issues the following subset of the possible ACE
transactions:
• ReadClean: Issued when a cache line is allocated.
• CleanUnique: Issued when an SWX instruction is executed as part of an exclusive access
sequence.
• ReadOnce: Issued when the cache is off, or if the MMU Inhibit Caching bit is set for the
cache line.
• WriteUnique: Issued whenever a store instruction performs a write.
• CleanInvalid: Issued when a
WDC.EXT.FLUSH instruction is executed.
• MakeInvalid: Issued when a
WDC.EXT.CLEAR instruction is executed.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module