Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 23
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
• A conditional sequence begins with an LWX instruction. It can be followed by memory
accesses and/or computations on the loaded value. The sequence ends with an SWX
instruction. In most cases, failure of the SWX instruction should cause a branch back to
the LWX for a repeated attempt.
• An LWX instruction can be left unpaired when executing certain synchronization
primitives if the value loaded by the LWX is not zero. An implementation of Test and Set
exemplifies this:
loop: lwx r5,r3,r0 ; load and reserve
bnei r5,next ; branch if not equal to zero
addik r5,r5,1 ; increment value
swx r5,r3,r0 ; try to store non-zero value
addic r5,r0,0 ; check reservation
bnei r5,loop ; loop if reservation lost
next:
• Performance can be improved by minimizing looping on an LWX instruction that fails to
return a desired value. Performance can also be improved by using an ordinary load
instruction to do the initial value check. An implementation of a spinlock exemplifies
this:
loop: lw r5,r3,r0 ; load the word
bnei r5,loop ; loop back if word not equal to 0
lwx r5,r3,r0 ; try reserving again
bnei r5,loop ; likely that no branch is needed
addik r5,r5,1 ; increment value
swx r5,r3,r0 ; try to store non-zero value
addic r5,r0,0 ; check reservation
bnei r5,loop ; loop if reservation lost
• Minimizing the looping on an LWX/SWX instruction pair increases the likelihood that
forward progress is made. The old value should be tested before attempting the store.
If the order is reversed (store before load), more SWX instructions are executed and
reservations are more likely to be lost between the LWX and SWX instructions.
Self-modifying Code
When using self-modifying code software must ensure that the modified instructions have
been written to memory prior to fetching them for execution. There are several aspects to
consider:
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module