Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 24
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
• The instructions to be modified could already have been fetched prior to modification:
-
Into the instruction prefetch buffer
-
Into the instruction cache, if it is enabled
-
Into a stream buffer, if instruction cache stream buffers are used
-
Into the instruction cache, and then saved in a victim buffer, if victim buffers are
used.
To ensure that the modified code is always executed instead of the old unmodified
code, software must handle all these cases.
• If one or more of the instructions to be modified is a branch, and the branch target
cache is used, the branch target address might have been cached.
To avoid using the cached branch target address, software must ensure that the branch
target cache is cleared prior to executing the modified code.
• The modified instructions might not have been written to memory prior to execution:
-
They might be en-route to memory, in temporary storage in the interconnect or the
memory controller.
-
They might be stored in the data cache, if write-back cache is used.
-
They might be saved in a victim buffer, if write-back cache and victim buffers are
used.
Software must ensure that the modified instructions have been written to memory before
being fetched by the processor.
The annotated code below shows how each of the above issues can be addressed. This code
assumes that both instruction cache and write-back data cache is used. If not, the
corresponding instructions can be omitted.
The following code exemplifies storing a modified instruction:
swi r5,r6,0 ; r5 = new instruction
; r6 = physical instruction address
wdc.flush r6,r0 ; flush write-back data cache line
mbar 1 ; ensure new instruction is written to memory
wic r7,r0 ; invalidate line, empty stream & victim buffers
; r7 = virtual instruction address
mbar 2 ; empty prefetch buffer, clear branch target cache
The physical and virtual addresses above are identical, unless MMU virtual mode is used. If
the MMU is enabled, the code sequences must be executed in real mode, because WIC and
WDC are privileged instructions. The first instruction after the code sequences above must
not be modified, because it might have been prefetched.
Send Feedback

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module