Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 91
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
The value of a floating-point number v in MicroBlaze has the following interpretation:
1. If exponent = 255 and fraction <> 0, then v= NaN, regardless of the sign bit
2. If exponent = 255 and fraction = 0, then v= (-1)
sign
* ∞
3. If 0 < exponent < 255, then v = (-1)
sign
* 2
(exponent-127)
* (1.fraction)
4. If exponent = 0 and fraction <> 0, then v = (-1)
sign
* 2
-126
* (0.fraction)
5. If exponent = 0 and fraction = 0, then v = (-1)
sign
* 0
For practical purposes only 3 and 5 are useful, while the others all represent either an error
or numbers that can no longer be represented with full precision in a 32 bit format.
Rounding
The MicroBlaze FPU only implements the default rounding mode, “Round-to-nearest”,
specified in IEEE 754. By definition, the result of any floating-point operation should return
the nearest single precision value to the infinitely precise result. If the two nearest
representable values are equally near, then the one with its least significant bit zero is
returned.
Operations
All MicroBlaze FPU operations use the processors general purpose registers rather than a
dedicated floating-point register file, see
General Purpose Registers.
Arithmetic
The FPU implements the following floating-point operations:
•addition, fadd
•subtraction, frsub
• multiplication, fmul
• division, fdiv
• square root, fsqrt (available if
C_USE_FPU = 2, EXTENDED)
X-Ref Target - Figure 2-24
Figure 2-24: IEEE 754 Single Precision Format
31
9
fraction
exponent
10
sign
X19761-082517
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module