Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 92
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Comparison
The FPU implements the following floating-point comparisons:
• compare less-than, fcmp.lt
•compare equal, fcmp.eq
• compare less-or-equal, fcmp.le
• compare greater-than, fcmp.gt
• compare not-equal, fcmp.ne
• compare greater-or-equal, fcmp.ge
• compare unordered, fcmp.un (used for NaN)
Conversion
The FPU implements the following conversions (available if C_USE_FPU = 2, EXTENDED):
• convert from signed integer to floating-point, flt
• convert from floating-point to signed integer, fint
Exceptions
The floating-point unit uses the regular hardware exception mechanism in MicroBlaze.
When enabled, exceptions are thrown for all the IEEE standard conditions: underflow,
overflow, divide-by-zero, and illegal operation, as well as for the MicroBlaze specific
exception: denormalized operand error.
A floating-point exception inhibits the write to the destination register (Rd). This allows a
floating-point exception handler to operate on the uncorrupted register file.
Software Support
The SDK compiler system, based on GCC, provides support for the floating-point Unit
compliant with the MicroBlaze API. Compiler flags are automatically added to the GCC
command line based on the type of FPU present in the system, when using SDK.
All double-precision operations are emulated in software. Be aware that the xil_printf()
function does not support floating-point output. The standard C library
printf() and
related functions do support floating-point output, but will increase the program code size.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module