Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 93
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Libraries and Binary Compatibility
The SDK compiler system only includes software floating-point C runtime libraries. To take
advantage of the hardware FPU, the libraries must be recompiled with the appropriate
compiler switches.
For all cases where separate compilation is used, it is very important that you ensure the
consistency of FPU compiler flags throughout the build.
Operator Latencies
The latencies of the various operations supported by the FPU are listed in Chapter 5,
“MicroBlaze Instruction Set Architecture.” The FPU instructions are not pipelined, so only
one operation can be ongoing at any time.
C Language Programming
To gain maximum benefit from the FPU without low-level assembly-language
programming, it is important to consider how the C compiler will interpret your source
code. Very often the same algorithm can be expressed in many different ways, and some are
more efficient than others.
Immediate Constants
Floating-point constants in C are double-precision by default. When using a single-
precision FPU, careless coding could result in double-precision software emulation routines
being used instead of the native single-precision instructions. To avoid this, explicitly
specify (by cast or suffix) that immediate constants in your arithmetic expressions are
single-precision values.
For example:
float x = 0.0;
...
x += (float)1.0; /* float addition */
x += 1.0F; /* alternative to above */
x += 1.0; /* warning - uses double addition! */
Note that the GNU C compiler can be instructed to treat all floating-point constants as
single-precision (contrary to the ANSI C standard) by supplying the compiler flag -fsingle-
precision-constants.
Avoiding Unnecessary Casting
While conversions between floating-point and integer formats are supported in hardware
by the FPU, when
C_USE_FPU is set to 2 (Extended), it is still best to avoid them when
possible.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module