Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 94
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
The following not-recommended example calculates the sum of squares of the integers
from 1 to 10 using floating-point representation:
float sum, t;
int i;
sum = 0.0f;
for (i = 1; i <= 10; i++) {
t = (float)i;
sum += t * t;
}
The above code requires a cast from an integer to a float on each loop iteration. This can be
rewritten as:
float sum, t;
int i;
t = sum = 0.0f;
for(i = 1; i <= 10; i++) {
t += 1.0f;
sum += t * t;
}
Note: The compiler is not at liberty to perform this optimization in general, as the two code
fragments above might give different results in some cases (for example, very large t).
Using Square Root Runtime Library Function
The standard C runtime math library functions operate using double-precision arithmetic.
When using a single-precision FPU, calls to the square root functions (
sqrt()) result in
inefficient emulation routines being used instead of FPU instructions:
#include <math.h>
...
float x=-1.0F;
...
x = sqrt(x); /* uses double precision */
Here the math.h header is included to avoid a warning message from the compiler.
When used with single-precision data types, the result is a cast to double, a runtime library
call is made (which does not use the FPU) and then a truncation back to float is performed.
The solution is to use the non-ANSI function sqrtf() instead, which operates using single
precision and can be carried out using the FPU. For example:
#include <math.h>
...
float x=-1.0F;
...
x = sqrtf(x); /* uses single precision */
Note: When compiling this code, the compiler flag -fno-math-errno (in addition to
-mhard-float and -mxl-float-sqrt) must be used, to ensure that the compiler does not
generate unnecessary code to handle error conditions by updating the errno variable.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module