Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 119
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
In this case, fault tolerance is automatically enabled in MicroBlaze by the tools, when the
system is generated. This means that nothing else needs to be configured to enable ECC
support and MicroBlaze fault tolerance.
ECC must either be enabled or disabled in all Controllers, which is enforced by a DRC.
It is possible to manually override fault tolerance support in MicroBlaze, by explicitly
disabling
C_FAULT_TOLERANT in the MicroBlaze configuration dialog. This is not
recommended, unless no block RAM is used in MicroBlaze, and there is no need to handle
bus exceptions from uncorrectable ECC errors.
Features
An overview of all MicroBlaze fault tolerance features is given here. Further details on each
feature can be found in the following sections:
• Instruction Cache
• Data Cache
• UTLB Management
• Branch Target Cache
• Exception Causes
The LMB BRAM Interface Controller v4.0 or later provides the LMB ECC implementation. For
details, including performance and resource utilization, see the LogiCORE IP LMB BRAM
Interface Controller Product Guide (PG112)
[Ref 3].
Instruction and Data Cache Protection
To protect the block RAM in the Instruction and Data Cache, parity is used. When a parity
error is detected, the corresponding cache line is invalidated. This forces the cache to reload
the correct value from external memory. Parity is checked whenever a cache hit occurs.
Note: This scheme only works for write-through, and thus write-back data cache is not available
when fault tolerance is enabled. This is enforced by a DRC.
When new values are written to a block RAM in the cache, parity is also calculated and
written. One parity bit is used for the tag, one parity bit for the instruction cache data, and
one parity bit for each word in a data cache line.
In many cases, enabling fault tolerance does not increase the required number of cache
block RAMs, since spare bits can be used for the parity. Any increase in resource utilization,
in particular number of block RAMs, can easily be seen in the MicroBlaze configuration
dialog, when enabling fault tolerance.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module