Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 74
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
• For all other exceptions the register R17 is loaded with the program counter value of
the subsequent instruction, unless the exception is caused by an instruction in a branch
delay slot. If the exception is caused by an instruction in a branch delay slot, the
ESR[DS] bit is set. In this case the exception handler should resume execution from the
branch target address stored in BTR.
The EE and EIP bits in MSR are automatically reverted when executing the RTED instruction.
The VM and UM bits in MSR are automatically reverted from VMS and UMS when executing
the
RTED, RTBD, and RTID instructions.
Exception Priority
When two or more exceptions occur simultaneously, they are handled in the following
order, from the highest priority to the lowest:
• Instruction Bus Exception
• Instruction TLB Miss Exception
• Instruction Storage Exception
• Illegal Opcode Exception
• Privileged Instruction Exception or Stack Protection Violation Exception
• Data TLB Miss Exception
• Data Storage Exception
• Unaligned Exception
• Data Bus Exception
• Divide Exception
•FPU Exception
•Stream Exception
Exception Causes
• Stream Exception: The AXI4-Stream exception is caused by executing a get or getd
instruction with the ‘e’ bit set to ‘1’ when there is a control bit mismatch.
• Instruction Bus Exception: The instruction bus exception is caused by errors when
reading data from memory.
-
The instruction peripheral AXI4 interface (M_AXI_IP) exception is caused by an error
response on
M_AXI_IP_RRESP.
-
The instruction cache AXI4 interface (M_AXI_IC) is caused by an error response on
M_AXI_IC_RRESP. The exception can only occur when C_ICACHE_ALWAYS_USED is set
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module