Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 75
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
to 1 and the cache is turned off, or if the MMU Inhibit Caching bit is set for the
address. In all other cases the response is ignored.
-
The instructions side local memory (ILMB) can only cause instruction bus exception
when either an uncorrectable error occurs in the LMB memory, as indicated by the
IUE signal, or C_ECC_USE_CE_EXCEPTION is set to 1 and a correctable error occurs
in the LMB memory, as indicated by the
ICE signal.
• Illegal Opcode Exception: The illegal opcode exception is caused by an instruction
with an invalid major opcode (bits 0 through 5 of instruction). Bits 6 through 31 of the
instruction are not checked. Optional processor instructions are detected as illegal if
not enabled. If the optional feature
C_OPCODE_0x0_ILLEGAL is enabled, an illegal
opcode exception is also caused if the instruction is equal to 0x00000000.
• Data Bus Exception: The data bus exception is caused by errors when reading data
from memory or writing data to memory.
-
The data peripheral AXI4 interface (M_AXI_DP) exception is caused by an error
response on
M_AXI_DP_RRESP or M_AXI_DP_BRESP.
-
The data cache AXI4 interface (M_AXI_DC) exception is caused by:
- An error response on
M_AXI_DC_RRESP or M_AXI_DC_BRESP,
-
OKAY response on M_AXI_DC_RRESP in case of an exclusive access using LWX.
The exception can only occur when
C_DCACHE_ALWAYS_USED is set to 1 and the
cache is turned off, when an exclusive access using
LWX or SWX is performed, or if the
MMU Inhibit Caching bit is set for the address. In all other cases the response is
ignored.
-
The data side local memory (DLMB) can only cause instruction bus exception when
either an uncorrectable error occurs in the LMB memory, as indicated by the
DUE
signal, or
C_ECC_USE_CE_EXCEPTION is set to 1 and a correctable error occurs in the
LMB memory, as indicated by the
DCE signal. An error can occur for all read
accesses, and for byte and halfword write accesses.
• Unaligned Exception: The unaligned exception is caused by a word access where the
address to the data bus has bits 30 or 31 set, or a half-word access with bit 31 set.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module