Xilinx MicroBlaze - Page 76

MicroBlaze Processor Reference Guide 76
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
• Divide Exception: The divide exception is caused by an integer division (idiv or
idivu) where the divisor is zero, or by a signed integer division (idiv) where overflow
occurs (-2147483648 / -1).
• FPU Exception: An FPU exception is caused by an underflow, overflow, divide-by-zero,
illegal operation, or denormalized operand occurring with a floating-point instruction.
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Underflow occurs when the result is denormalized.
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Overflow occurs when the result is not-a-number (NaN).
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The divide-by-zero FPU exception is caused by the rA operand to fdiv being zero
when rB is not infinite.
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Illegal operation is caused by a signaling NaN operand or by illegal infinite or zero
operand combinations.
• Privileged Instruction Exception: The Privileged Instruction exception is caused by an
attempt to execute a privileged instruction in User Mode.
• Stack Protection Violation Exception: A Stack Protection Violation exception is
caused by executing a load or store instruction using the stack pointer (register R1) as
rA with an address outside the stack boundaries defined by the special Stack Low and
Stack High registers, causing a stack overflow or a stack underflow.
• Data Storage Exception: The Data Storage exception is caused by an attempt to
access data in memory that results in a memory-protection violation.
• Instruction Storage Exception: The Instruction Storage exception is caused by an
attempt to access instructions in memory that results in a memory-protection violation.
• Data TLB Miss Exception: The Data TLB Miss exception is caused by an attempt to
access data in memory, when a valid Translation Look-Aside Buffer entry is not present,
and virtual protected mode is enabled.
• Instruction TLB Miss Exception: The Instruction TLB Miss exception is caused by an
attempt to access instructions in memory, when a valid Translation Look-Aside Buffer
entry is not present, and virtual protected mode is enabled.
Should an Instruction Bus Exception, Illegal Opcode Exception, or Data Bus Exception occur
when
C_FAULT_TOLERANT is set to 1, and an exception is in progress (that is MSR[EIP] set
and MSR[EE] cleared), the pipeline is halted, and the external signal
MB_Error is set.
Imprecise Exceptions
Normally all exceptions in MicroBlaze are precise, meaning that any instructions in the
pipeline after the instruction causing an exception are invalidated, and have no effect.
When C_IMPRECISE_EXCEPTIONS is set to 1 (ECC) an Instruction Bus Exception or Data Bus
Exception caused by ECC errors in LMB memory is not precise, meaning that a subsequent
memory access instruction in the pipeline might be executed. If this behavior is acceptable,
the maximum frequency can be improved by setting this parameter to 1.
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