Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 77
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Equivalent Pseudocode
ESR[DS] ← exception in delay slot
if ESR[DS] then
BTR
← branch target PC
if MMU exception then
if branch preceded by IMM then
r17
← PC - 8
else
r17
← PC - 4
else
r17
← invalid value
else if MMU exception then
if instruction preceded by IMM then
r17
← PC - 4
else
r17 ← PC
else
r17
← PC + 4
PC ← C_BASE_VECTORS + 0x00000020
MSR[EE]
← 0, MSR[EIP]← 1
MSR[UMS] ← MSR[UM], MSR[UM] ← 0, MSR[VMS] ← MSR[VM], MSR[VM] ← 0
ESR[EC] ← exception specific value
ESR[ESS]
← exception specific value
EAR ← exception specific value
FSR ← exception specific value
Reservation ← 0
Breaks
There are two kinds of breaks:
• Hardware (external) breaks
• Software (internal) breaks
Hardware Breaks
Hardware breaks are performed by asserting the external break signal (that is, the Ext_BRK
and
Ext_NM_BRK input ports). On a break, the instruction in the execution stage completes
while the instruction in the decode stage is replaced by a branch to the break vector
(address
C_BASE_VECTORS + 0x18).
The break return address (the PC associated with the instruction in the decode stage at the
time of the break) is automatically loaded into general purpose register R16. MicroBlaze
also sets the Break In Progress (
BIP) flag in the Machine Status Register (MSR).
A normal hardware break (that is, the Ext_BRK input port) is only handled when MSR[BIP]
and MSR[EIP] are set to 0 (that is, there is no break or exception in progress). The Break In
Progress flag disables interrupts. A non-maskable break (that is, the
Ext_NM_BRK input
port) is always handled immediately.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module