Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 78
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
The BIP bit in the MSR is automatically cleared when executing the RTBD instruction.
The Ext_BRK signal must be kept asserted until the break has occurred, and deasserted
before the RTBD instruction is executed. The
Ext_NM_BRK signal must only be asserted one
clock cycle.
Software Breaks
To perform a software break, use the brk and brki instructions. Refer to Chapter 5,
MicroBlaze Instruction Set Architecture for detailed information on software breaks.
As a special case, when C_DEBUG_ENABLED is greater than zero, and “brki rD,0x18” is
executed, a software breakpoint is signaled to the debugger; for example, the Xilinx System
Debugger (XSDB) tool, irrespective of the value of
C_BASE_VECTORS. In this case the BIP bit
in the MSR is not set.
Latency
The time it takes the MicroBlaze processor to enter a break service routine from the time
the break occurs depends on the instruction currently in the execution stage and the
latency to the memory storing the break vector.
Equivalent Pseudocode
r16 ← PC
PC ← C_BASE_VECTORS + 0x00000018
MSR[BIP]
← 1
MSR[UMS] ← MSR[UM], MSR[UM] ← 0, MSR[VMS] ← MSR[VM], MSR[VM] ← 0
Reservation ← 0
Interrupt
MicroBlaze supports one external interrupt source (connected to the Interrupt input port).
The processor only reacts to interrupts if the Interrupt Enable (IE) bit in the Machine Status
Register (MSR) is set to 1. On an interrupt, the instruction in the execution stage completes
while the instruction in the decode stage is replaced by a branch to the interrupt vector.
This is either address
C_BASE_VECTORS + 0x10, or with low-latency interrupt mode, the
address supplied by the Interrupt Controller.
The interrupt return address (the PC associated with the instruction in the decode stage at
the time of the interrupt) is automatically loaded into general purpose register R14. In
addition, the processor also disables future interrupts by clearing the IE bit in the MSR. The
IE bit is automatically set again when executing the RTID instruction.
Interrupts are ignored by the processor if either of the break in progress (BIP) or exception
in progress (
EIP) bits in the MSR are set to 1.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module