Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 79
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
By using the parameter C_INTERRUPT_IS_EDGE, the external interrupt can either be set to
level-sensitive or edge-triggered:
• When using level-sensitive interrupts, the Interrupt input must remain set until
MicroBlaze has taken the interrupt, and jumped to the interrupt vector. Software must
acknowledge the interrupt at the source to clear it before returning from the interrupt
handler. If not, the interrupt is taken again, as soon as interrupts are enabled when
returning from the interrupt handler.
• When using edge-triggered interrupts, MicroBlaze detects and latches the
Interrupt
input edge, which means that the input only needs to be asserted one clock cycle. The
interrupt input can remain asserted, but must be deasserted at least one clock cycle
before a new interrupt can be detected. The latching of an edge-triggered interrupt is
independent of the IE bit in MSR. Should an interrupt occur while the IE bit is 0, it will
immediately be serviced when the IE bit is set to 1.
With periodic interrupt sources, such as the FIT Timer IP core, that do not have a method to
clear the interrupt from software, it is recommended to use edge-triggered interrupts.
Low-latency Interrupt Mode
A low-latency interrupt mode is available, which allows the Interrupt Controller to directly
supply the interrupt vector for each individual interrupt (using the
Interrupt_Address
input port). The address of each fast interrupt handler must be passed to the Interrupt
Controller when initializing the interrupt system. When a particular interrupt occurs, this
address is supplied by the Interrupt Controller, which allows MicroBlaze to directly jump to
the handler code.
With this mode, MicroBlaze also directly sends the appropriate interrupt acknowledge to
the Interrupt Controller (using the
Interrupt_Ack output port), although it is still the
responsibility of the Interrupt Service Routine to acknowledge level sensitive interrupts at
the source.
This information allows the Interrupt Controller to acknowledge interrupts appropriately,
both for level-sensitive and edge-triggered interrupt.
To inform the Interrupt Controller of the interrupt handling events, Interrupt_Ack is set to:
• 01: When MicroBlaze jumps to the interrupt handler code,
• 10: When the RTID instruction is executed to return from interrupt,
• 11: When MSR[IE] is changed from 0 to 1, which enables interrupts again.
The Interrupt_Ack output port is active during one clock cycle, and is then reset to 00.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module