Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 73
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Reset
When a Reset or Debug_Rst
(1)
occurs, MicroBlaze flushes the pipeline and starts fetching
instructions from the reset vector (address 0x0). Both external reset signals are active high
and should be asserted for a minimum of 16 cycles. See
MicroBlaze Core Configurability in
Chapter 3 for more information on the MSR reset value parameters.
Equivalent Pseudocode
PC ← C_BASE_VECTORS + 0x00000000
MSR ← C_RESET_MSR_IE << 2 | C_RESET_MSR_BIP << 4 | C_RESET_MSR_ICE << 6 |
C_RESET_MSR_DCE << 8 | C_RESET_MSR_EE << 9 | C_RESET_MSR_EIP << 10
EAR
← 0; ESR ← 0; FSR ← 0
PID ← 0; ZPR ← 0; TLBX ← 0
Reservation ← 0
Hardware Exceptions
MicroBlaze can be configured to trap the following internal error conditions: illegal
instruction, instruction and data bus error, and unaligned access. The divide exception can
only be enabled if the processor is configured with a hardware divider (
C_USE_DIV=1).
When configured with a hardware floating-point unit (C_USE_FPU>0), it can also trap the
following floating-point specific exceptions: underflow, overflow, float division-by-zero,
invalid operation, and denormalized operand error.
When configured with a hardware memory management unit (MMU), it can also trap the
following memory management specific exceptions: Illegal Instruction Exception, Data
Storage Exception, Instruction Storage Exception, Data TLB Miss Exception, and Instruction
TLB Miss Exception.
A hardware exception causes MicroBlaze to flush the pipeline and branch to the hardware
exception vector (address
C_BASE_VECTORS + 0x20). The execution stage instruction in the
exception cycle is not executed.
The exception also updates the general purpose register R17 in the following manner:
• For the MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data
TLB Miss Exception, Instruction TLB Miss Exception) the register R17 is loaded with the
appropriate program counter value to re-execute the instruction causing the exception
upon return. The value is adjusted to return to a preceding
IMM instruction, if any. If the
exception is caused by an instruction in a branch delay slot, the value is adjusted to
return to the branch instruction, including adjustment for a preceding
IMM instruction,
if any.
1. Reset input controlled by the debugger using MDM.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module