Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 117
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Trace Interface Overview
The MicroBlaze trace interface exports a number of internal state signals for performance
monitoring and analysis.
RECOMMENDED: Xilinx recommends that users only use the trace interface through Xilinx developed
analysis cores.
This interface is not guaranteed to be backward compatible in future releases of MicroBlaze.
See
Table 3-16 in Chapter 3, MicroBlaze Signal Interface Description for a list of exported
signals.
Send Feedback

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module