Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 98
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
A typical procedure to follow when initializing and using the performance monitoring
counters is delineated in the steps below.
1. Initialize the events to be monitored:
-
Use the Performance Command Register (Table 2-44) to reset the selected counter
to the first counter, by setting the Reset bit.
-
Write the desired event numbers for all counters in order, using the Performance
Control Register (Table 2-43). With the default configuration this means writing the
register five times for the event counters and then once for the latency counter.
2. Clear all counters and start monitoring using the Performance Command Register, by
setting the Clear and Start bits.
3. Run the program or function to be monitored.
4. Sample counters and stop monitoring using the Performance Command Register, by
setting the Sample and Stop bits.
5. Read the results from all counters:
-
Use the Performance Command Register to reset the selected counter to the first
counter, by setting the Reset bit.
-
Read the status for all counters in order, using the Performance Counter Status
Register (Table 2-45). With the default configuration this means reading the register
five times for the event counters and then once for the latency counter. Ensure that
the result is valid by checking that the overflow and full bits are not set.
-
Use the Performance Command Register to reset the selected counter to the first
counter, by setting the Reset bit.
-
Read the counter items for all counters in order, using the Performance Counter
Data Read Register (Table 2-46). With the default configuration this means reading
the register five times for the event counters and then four times for the latency
counter as described in Table 2-47.
6. Calculate the final results, depending on the measured events, for example:
-
Use the formulas above to determine the mean latency and standard deviation for
any measured latency.
-
The clock cycles per instruction (CPI) can be calculated by E
30
/ E
0
.
-
The instruction and data cache hit rates can be calculated by E
11
/ E
10
and E
47
/ E
46
.
-
The instruction cache miss latency is determined by (E
60
(ΣL) - E
60
(N)) / (E
10
- E
11
),
and equivalent formulas can be used to determine the data cache read and write
miss latencies.
-
The ratio of floating-point instructions in a program is E
29
/E
0
.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module