Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 166
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_DP_ARVALID 721 std_logic
M_AXI_DP_RREADY 722 std_logic
Mn_AXIS_TLAST 723 + n * 35 std_logic
Mn_AXIS_TDATA 758 + n * 35 to
789 + n * 35
std_logic_vector
Mn_AXIS_TVALID 790 + n * 35 std_logic
Sn_AXIS_TREADY 791 + n * 35 std_logic
M_AXI_IC_AWID 1283 std_logic
M_AXI_IC_AWADDR 1284 to 1347 std_logic_vector
M_AXI_IC_AWLEN 1348 to 1355 std_logic_vector
M_AXI_IC_AWSIZE 1356 to 1358 std_logic_vector
M_AXI_IC_AWBURST 1359 to 1360 std_logic_vector
M_AXI_IC_AWLOCK 1361 std_logic
M_AXI_IC_AWCACHE 1362 to 1365 std_logic_vector
M_AXI_IC_AWPROT 1366 to 1368 std_logic_vector
M_AXI_IC_AWQOS 1369 to 1372 std_logic_vector
M_AXI_IC_AWVALID 1373 std_logic
M_AXI_IC_AWUSER 1374 to 1378 std_logic_vector
M_AXI_IC_AWDOMAIN
1
1379 to 1380 std_logic_vector
M_AXI_IC_AWSNOOP
1
1381 to 1383 std_logic_vector
M_AXI_IC_AWBAR
1
1384 to 1385 std_logic_vector
M_AXI_IC_WDATA 1386 to 1897 std_logic_vector
M_AXI_IC_WSTRB 1898 to 1961 std_logic_vector
M_AXI_IC_WLAST 1962 std_logic
M_AXI_IC_WVALID 1963 std_logic
M_AXI_IC_WUSER 1964 std_logic
M_AXI_IC_BREADY 1965 std_logic
M_AXI_IC_WACK 1966 std_logic
M_AXI_IC_ARID 1967 std_logic_vector
M_AXI_IC_ARADDR 1968 to 2031 std_logic_vector
M_AXI_IC_ARLEN 2032 to 2039 std_logic_vector
M_AXI_IC_ARSIZE 2040 to 2042 std_logic_vector
M_AXI_IC_ARBURST 2043 to 2044 std_logic_vector
M_AXI_IC_ARLOCK 2045 std_logic
M_AXI_IC_ARCACHE 2046 to 2049 std_logic_vector
M_AXI_IC_ARPROT 2050 to 2052 std_logic_vector
M_AXI_IC_ARQOS 2053 to 2056 std_logic_vector
M_AXI_IC_ARVALID 2057 std_logic
M_AXI_IC_ARUSER 2058 to 2062 std_logic_vector
M_AXI_IC_ARDOMAIN
1
2063 to 2064 std_logic_vector
Table 3-14: MicroBlaze Lockstep Comparison Signals (Cont’d)
Signal Name Bus Index Range VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module