Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 128
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
The redundant MicroBlaze processors are functionally identical, except for debug logic and
associated signals.The outputs from the master MicroBlaze core drive the peripherals in the
system. The slave MicroBlaze core only has inputs connected; all outputs are left open.
The system contains the basic building block for designing a complete fault tolerant
application, where one or more additional blocks must be added to provide redundancy.
This use case is illustrated in the following figure.
X-Ref Target - Figure 2-42
Figure 2-42: Lockstep Error Detection Application
BRAM
DLMB
Bram Controller
ILMB
Bram Controller
MicroBlaze
Master
Debug
MicroBlaze
Debug Module
MicroBlaze
Slave
Debug
Comparator
I/O Interfaces
External
Memory
Interfaces
Error Reset
Inputs
C_LOCKSTEP_SLAVE=0
C_LOCKSTEP_SLAVE=1
Lockstep_Out
Lockstep_Out
Outputs
Inputs
Inputs
X19778-091317
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module