Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 84
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
WIC Instruction
The optional WIC instruction (C_ALLOW_ICACHE_WR=1) is used to invalidate cache lines in
the instruction cache from an application. For a detailed description, see
Chapter 5,
MicroBlaze Instruction Set Architecture.
The WIC instruction can also be used together with parity protection to periodically
invalidate entries the cache, to avoid accumulating errors.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module