Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 3
UG984 (v2018.2) June 21, 2018 www.xilinx.com
04/15/2015
2015.1
Updated for Vivado 2015.1 release:
• Included description of 16 word cache line length, new in version 9.5.
• Added version 9.5 to MicroBlaze release version code in PVR.
• Corrected description of supported endianness and parameter C_ENDIANNESS.
• Corrected description of outstanding reads for instruction and data cache.
• Updated FPGA configuration memory protection document reference [Ref 5].
• Corrected Bus Index Range definitions for Lockstep Comparison in Table 3-14.
• Clarified registers altered for IDIV instruction.
• Corrected PVR assembler mnemonics for MFS instruction.
• Updated performance and resource utilization for 2015.1.
• Added references to training resources.
10/01/2014
2014.3
Updated for Vivado 2014.3 release:
• Corrected semantic description for PCMPEQ and PCMPNE in Table 2.1.
• Added version 9.4 to MicroBlaze release version code in PVR.
• Included description of external program trace, new in version 9.4
04/02/2014
2014.1
Updated for Vivado 2014.1 release:
• Added v9.3 to MicroBlaze release version code in PVR.
• Clarified availability and behavior of stack protection registers.
• Corrected description of LMB instruction and data bus exception.
• Included description of extended debug features, new in version 9.3: performance
monitoring, program trace and non-intrusive profiling.
• Included definition of Reset Mode signals, new in version 9.3.
• Clarified how the AXI4-Stream TLAST signal is handled.
• Added UltraScale and updated performance and resource utilization for 2014.1.
12/18/2013
2013.4
Updated for Vivado 2013.4 release.
10/02/2013
2013.3
Updated for Vivado 2013.3 release.
06/19/2013
2013.2
Updated for Vivado 2013.2 release.
03/20/2013
2013.1
Initial Xilinx release. This User Guide is derived from UG081.
Date Version Revision
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module