Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 57
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
CAUTION! It is strongly discouraged to do this, unless absolutely necessary for performance reasons,
because it allows application processes to interfere with each other.
When setting the parameter C_MMU_PRIVILEGED_INSTR to 2 or 3, the extended address
instructions
LBUEA, LHUEA, LWEA, SBEA, SHEA, and SWEA are not considered privileged, and
will bypass the MMU translation, treating the extended address as a physical address. This
is useful to run software in virtual mode while still having direct access to the full physical
address space, but is discouraged in all cases where protection between application
processes is necessary.
There are six ways to leave user mode and virtual mode:
1. Hardware generated reset (including debug reset)
2. Hardware exception
3. Non-maskable break or hardware break
4. Interrupt
5. Executing "
BRALID Re,C_BASE_VECTORS + 0x8” to perform a user vector exception
6. Executing the software break instructions “
BRKI” jumping to physical address
C_BASE_VECTORS + 0x8 or C_BASE_VECTORS + 0x18
In all of these cases, except hardware generated reset, the user mode and virtual mode
status is saved in the MSR UMS and VMS bits.
Application (user-mode) programs transfer control to system-service routines (privileged
mode programs) using the
BRALID or BRKI instruction, jumping to physical address
C_BASE_VECTORS + 0x8. Executing this instruction causes a system-call exception to occur.
The exception handler determines which system-service routine to call and whether the
calling application has permission to call that service. If permission is granted, the
exception handler performs the actual procedure call to the system-service routine on
behalf of the application program.
The execution environment expected by the system-service routine requires the execution
of prologue instructions to set up that environment. Those instructions usually create the
block of storage that holds procedural information (the activation record), update and
initialize pointers, and save volatile registers (the registers that the system-service routine
uses). Prologue code can be inserted by the linker when creating an executable module, or
it can be included as stub code in either the system-call interrupt handler or the system-
library routines.
Returns from the system-service routine reverse the process described above. Epilogue
code is executed to unwind and deallocate the activation record, restore pointers, and
restore volatile registers. The interrupt handler executes a return from exception instruction
(
RTED) to return to the application.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module