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General| Number of Data Lanes | 1, 2, 3, or 4 |
|---|---|
| AXI4-Stream Interface | Yes |
| Clock Lane | 1 |
| Supported Data Types | RGB888, RGB666, RGB565, YUV422 |
| PHY Interface | D-PHY |
| Compliance | MIPI CSI-2 v1.3 |
| Supported MIPI CSI-2 Version | v1.3 |
| Supported Pixel Formats | RAW, RGB, YUV |
| Compatible FPGA Families | Xilinx UltraScale+, Xilinx 7 Series |
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