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General| Number of Data Lanes | 1, 2, 3, or 4 |
|---|---|
| AXI4-Stream Interface | Yes |
| Clock Lane | 1 |
| Supported Data Types | RGB888, RGB666, RGB565, YUV422 |
| PHY Interface | D-PHY |
| Compliance | MIPI CSI-2 v1.3 |
| Supported MIPI CSI-2 Version | v1.3 |
| Supported Pixel Formats | RAW, RGB, YUV |
| Compatible FPGA Families | Xilinx UltraScale+, Xilinx 7 Series |
Details the MIPI D-PHY and MIPI CSI-2 RX Controller cores, their features, and specifications.
Lists features not supported by the MIPI CSI-2 RX Subsystem, such as specific YUV data types and 8-lane support.
Provides details on license checkers, license types, and how to purchase the MIPI CSI-2 RX Subsystem.
Lists the MIPI Alliance standards and physical layer specifications for CSI-2 and D-PHY.
Details performance information, including D-PHY, Controller, and VFB latency calculations.
Guides users to performance and resource utilization details via a web page.
Describes the I/O signals for the MIPI CSI-2 RX Subsystem, including AXI and other interfaces.
Details the register map, address offsets, and core registers for the MIPI CSI-2 RX Controller.
Provides guidelines for connecting the subsystem, managing bandwidth, and configuring active lanes.
Explains how to share PLLs and BUFGs for multiple subsystem instances within the same I/O bank.
Details I/O planner features, HP I/O bank selection, and pin assignment for clock and data lanes.
Describes subsystem clocks, their frequencies, and relationships for video interface requirements.
Explains the subsystem's two reset ports (lite_aresetn, video_aresetn) and their impact on sub-cores.
Outlines the programming sequence for subsystem components and the address map example.
Guides on using Vivado tools to customize and generate the subsystem, including parameter settings.
Information on required XDC constraints, device/package/speed grade selections, and clock management.
Details on simulation support, Vivado simulation components, and synthesis/implementation steps.
Lists hardware components like ZCU102 board, sensors, and displays for the example design.
Demonstrates MIPI CSI-2 RX and DSI TX subsystems usage on ZCU102, showing data flow.
Prerequisites and step-by-step hardware setup instructions for the ZCU102 based example.
Instructions for building, programming, and executing the design on hardware using Xilinx System Debugger.
Step-by-step guide to creating a new Vivado project for the application example design.
Details hardware testing on Xilinx evaluation platforms and lists test scenarios on development boards.
Guides users to Xilinx Support website, documentation, and answer records for help.
Information on contacting Xilinx technical support and available Vivado debug features.
Provides debug steps for common hardware issues, including general checks and register monitoring.
Troubleshooting for AXI4-Lite and AXI4-Stream interfaces, including timing and sideband information.
Resources for support, documentation access via Navigator, and design hubs.
Lists documents providing supplemental material useful with the product guide.
Chronological record of document updates, including version numbers and revision details.
Contains legal notices, disclaimers, warranties, and information on product liability.
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