MIPI CSI-2 RX Subsystem v4.0 51
PG232 July 02, 2019 www.xilinx.com
Chapter 4
Design Flow Steps
This chapter describes customizing and generating the subsystem, constraining the
subsystem, and the simulation, synthesis and implementation steps that are specific to this
subsystem. More detailed information about the standard Vivado® design flows and the IP
integrator can be found in the following Vivado Design Suite user guides:
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
[Ref 8]
• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9]
• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 10]
• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 11]
Customizing and Generating the Subsystem
This section includes information about using Xilinx tools to customize and generate the
subsystem in the Vivado Design Suite.
If you are customizing and generating the subsystem in the Vivado IP integrator, see the
Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 8]
for detailed information. IP integrator might auto-compute certain configuration values
when validating or generating the design. To check whether the values do change, see the
description of the parameter in this chapter. To view the parameter value, run the
validate_bd_design command in the Tcl console.
You can customize the IP for use in your design by specifying values for the various
parameters associated with the subsystem using the following steps:
1. Select the IP from the Vivado IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or
right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9] and
the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 10].
Note:
Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE).
The layout depicted here might vary from the current version.
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