Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 50
PG232 July 02, 2019 www.xilinx.com
Chapter 3: Designing with the Subsystem
Note: The Active Lane bit field will not be updated if the RxByteClkHS is absent. This will be
indicated by the MIPI DPHY RX Clock lane being in stop state. After updating the active lanes field,
if the MIPI DPHY RX Clock lane is in stop state, you can continue without waiting for the Active Lane
bit field getting updated. Once the DPHY RX Clock Lane is out of stop state, you can check for this
field to get updated with programmed value
MIPI D-PHY IP Core Programming
See the MIPI D-PHY LogiCORE IP Product Guide (PG202) [Ref 3] for MIPI D-PHY IP core
programming details.
Send Feedback

Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English