Xilinx Vivado MIPI CSI-2 User Manual

MIPI CSI-2 RX Subsystem v4.0 59
PG232 July 02, 2019 www.xilinx.com
Chapter 4: Design Flow Steps
User Parameters
Tab l e 4 - 1 shows the relationship between the fields in the Vivado IDE and the User
Parameters (which can be viewed in the Tcl Console).
Table 4-1: Vivado IDE Parameter to User Parameter Relationship
Vivado IDE Parameter User Parameter Default Value
Pixel Format CMN_PXL_FORMAT RAW8
Serial Data Lanes CMN_NUM_LANES 1
Allowed VC CMN_VC All
Pixels Per Clock CMN_NUM_PIXELS 1
Enable AXI IIC(CCI) CMN_INC_IIC True
Include video Format Bridge (VFB) CMN_INC_VFB True
Support CSI Spec V2_0 C_EN_CSI_V2_0 False
Support VCX Feature C_EN_VCX False
Line Rate (Mb/s) DPY_LINE_RATE 1000
D-PHY Register Interface DPY_EN_REG_IF False
Calibration Mode C_CAL_MODE None
IDELAY Tap Value C_IDLY_TAP 1
Include IDELAYCTRL in Core C_SHARE_IDLYCTRL False
Enable 300 MHZ Clock for
IDELAYCTRL
C_EN_CLK300M False
Embedded non-image Interface CSI_EMB_NON_IMG False
Line Buffer Depth CSI_BUF_DEPTH 2048
Enable CRC C_CSI_EN_CRC True
Enable Active Lanes C_CSI_EN_ACTIVELANES False
Shared Logic Support Level 0
HP IO Bank Selection
HP_IO_BANK_SELECTIO
N
Value based on part selected.
Clock Lane CLK_LANE_IO_LOC Value based on part selected
Data Lane0 DATA_LANE0_IO_LOC Value based on part selected
Data Lane1 DATA_LANE1_IO_LOC Value based on part selected
Data Lane2 DATA_LANE2_IO_LOC Value based on part selected
Data Lane3 DATA_LANE3_IO_LOC Value based on part selected
HS_SETTLE Parameter (ns) C_HS_SETTLE_NS
145
Note:
Hidden parameter which can be
used to set HS_SETTLE value. Can be set
through Tcl flow.
Filter User Defined data types
C_CSI_FILTER_USERDATA
TYPE
False
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Xilinx Vivado MIPI CSI-2 Specifications

General

Brand	Xilinx
Model	Vivado MIPI CSI-2
Category	Receiver
Language	English